1. Technical Field of the Invention
The present invention relates generally to the field of transistor circuits and more particularly to a low voltage differential signal driver.
2. Description of the Related Art
Various standards have been promulgated in the field of data transmission. One type of data transmission is differential data transmission in which the difference in voltage levels between two signal lines form the transmitted signal. Differential data transmission is commonly used for data transmission rates greater than 100 megabits per second (Mbps) over long distances.
One application of differential data transmission is in a network using a bus to which multiple driver sources are attached. In one type of conventional circuit, the multiple drivers are connected to a common bus, in which only one driver may transmit at a time. The remaining drivers are typically in a high impedance state so as to not overload the bus. Since large positive and negative common mode signals may appear at the driver output terminals connected to a bus system, the maintenance of a high impedance over a wide common mode voltage range independent of whether the driver is powered or not, is desirable. Large positive and negative common mode signals seen across a bus can be caused by ground offsets among various drivers, which could drive the bus to voltage levels that could prove damaging to other devices attached on the bus.
In a multipoint system it is desirable to have a robust driver capable of withstanding a wide common mode range. Each driver in the system should also be very high impedance when disabled, so the leakage currents of disabled drivers do not degrade the transmission of data. Also, the driver should not be allowed to supply excessive currents which could damage the bus itself.
An example of a conventional low voltage differential signal (LVDS) driver circuit 100 is shown in FIG. 1A. The output terminals 102 and 104 form a pair of single-ended signals, one of which is the inverse of the other. The difference between these two signals constitutes the differential signal. This signal is essentially the voltage across the resistive load between y and z, which is either positive or negative depending on the direction of current flow across the load. The LVDS driver circuit 100 includes a direct current constant current source I0 and sink I1 coupled to voltage supply VCC and ground, respectively, and four n-channel metal, oxide semiconductor (NMOS) switches MN0, MN1, MN5 and MN6. The four transistor switches MN0, MN1, MN5 and MN6 are controlled by input voltage signals pos 106 and neg 108, and direct current through a load resistance between output pins y and z as indicated by arrows 110 and 112. The input voltage signals pos and neg are typically rail-to-rail voltage swings.
The gates of NMOS switches MN0 and MN6 are coupled together to receive input voltage signal pos. Similarly, the gates of NMOS switches MN1 and MN5 are coupled together to receive input voltage signal neg.
For operation of the LVDS driver circuit 100, two of the four NMOS switches turn on at a time to steer current from current source I0 to generate a voltage across a resistive load between outputs y and z. To steer current through the resistive load in the direction indicated by arrow 110, input signal neg goes high turning on NMOS switches MN1 and MN5. When input signal neg goes high, input signal pos goes low to keep NMOS switches MN0 and MN6 off during the time NMOS switches MN1 and MN5 are on. Conversely, to steer current through the resistive load in the direction indicated by arrow 112, input signal pos goes high and is applied to transistor switches MN0 and MN6 to make them conduct. Input signal neg goes low to keep MNOS switches MN1 and MN5 off during this time. As a result, a full differential output voltage swing can be achieved.
Circuit 120 is a typical common mode voltage regulator type circuit designed to regulate the center point of the driver circuit 100 during normal operation and FIG. 1B illustrates predriver logic which enables the pos and neg signals. The aforementioned drive circuit has a limited output voltage range over which the circuit functions properly.
The present invention achieves technical advantages in providing a differential signal to an external bus which can be driven by a plurality of devices. The invention includes a line driver configured to enable transmission of a differential output signal to the external bus. The invention further includes a voltage limiter which is electrically coupled to the line driver and the bus to limit voltage on the line driver. The voltage limiter and line driver can be enabled and disabled in response to voltage conditions on the external bus. A pull-up circuit can be provided to assist start-up of the line driver by preventing a negative voltage condition on the external bus.